-------------------------------------------------------------------------------
--
-- Title       : filter_Nkx16
-- Design      : Sirius_demod_v2
-- Author      : 
-- Company     : 
--
-------------------------------------------------------------------------------
--
-- File        : filter_Nkx16.vhd
-- Generated   : Fri Feb 10 22:02:06 2012
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {filter_Nkx16} architecture {filter_Nkx16}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity filter_Nkx16 is
    generic(Len_filter : INTEGER := 13);
    port(
        RST : in STD_LOGIC;
        CLK : in STD_LOGIC;
        CE : in STD_LOGIC;
        DIN0 : in STD_LOGIC_VECTOR(15 downto 0);
        DIN1 : in STD_LOGIC_VECTOR(15 downto 0);
        DOUT0 : out STD_LOGIC_VECTOR(23 downto 0);
        DOUT1 : out STD_LOGIC_VECTOR(23 downto 0)
        );
end filter_Nkx16;

--}} End of automatically maintained section

architecture filter_Nkx16 of filter_Nkx16 is
    -- Component declaration of the "subadder48(behavioral)" unit defined in
    -- file: "./../xilinxcoregen/SubAdder48.vhd"
    component subadder48
        generic(
            ACASCREG : INTEGER := 1;
            ALUMODEREG : INTEGER := 1;
            AREG : INTEGER := 1;
            AUTORESET_PATTERN_DETECT : BOOLEAN := FALSE;
            AUTORESET_PATTERN_DETECT_OPTINV : STRING := "MATCH";
            A_INPUT : STRING := "DIRECT";
            BCASCREG : INTEGER := 1;
            BREG : INTEGER := 1;
            B_INPUT : STRING := "DIRECT";
            CARRYINREG : INTEGER := 1;
            CARRYINSELREG : INTEGER := 0;
            CREG : INTEGER := 1;
            MASK : BIT_VECTOR := X"3FFFFFFFFFFF";
            MREG : INTEGER := 1;
            MULTCARRYINREG : INTEGER := 1;
            OPMODEREG : INTEGER := 0;
            PATTERN : BIT_VECTOR := X"000000000000";
            PREG : INTEGER := 1;
            SEL_MASK : STRING := "MASK";
            SEL_PATTERN : STRING := "PATTERN";
            SEL_ROUNDING_MASK : STRING := "SEL_MASK";
            USE_MULT : STRING := "NONE";
            USE_PATTERN_DETECT : STRING := "NO_PATDET";
            USE_SIMD : STRING := "ONE48");
        port(
            AB_IN : in STD_LOGIC_VECTOR(47 downto 0);
            ALUMODE_IN : in STD_LOGIC_VECTOR(3 downto 0);
            CARRYIN_IN : in STD_LOGIC;
            CE_IN : in STD_LOGIC;
            CLK_IN : in STD_LOGIC;
            C_IN : in STD_LOGIC_VECTOR(47 downto 0);
            RST_IN : in STD_LOGIC;
            P_OUT : out STD_LOGIC_VECTOR(47 downto 0));
    end component;
    signal din0_i, din1_i : std_logic_vector(47 downto 0):=(others => '0');
    signal din0_i_mid, din1_i_mid : std_logic_vector(47 downto 0):=(others => '0');
    signal din0_i_mid_2, din1_i_mid_2 : std_logic_vector(47 downto 0):=(others => '0');
    constant N : integer := 2**Len_filter;
    signal do0, do1 : std_logic_vector(47 downto 0):=(others => '0');
    signal sain0, sain1 : std_logic_vector(47 downto 0);
begin
    
    din0_i(Len_filter downto 0) <= (others => '0');
    din0_i(Len_filter+1+15 downto Len_filter+1+0) <= DIN0;
    din0_i(47 downto Len_filter+2+15) <= (others => DIN0(15));
    din1_i(Len_filter downto 0) <= (others => '0');
    din1_i(Len_filter+1+15 downto Len_filter+1+0) <= DIN1;
    din1_i(47 downto Len_filter+2+15) <= (others => DIN1(15));
    
    SUBADDER0 : subadder48
    generic map(ACASCREG => 0, ALUMODEREG => 0, AREG => 0, BCASCREG => 0, BREG => 0, CREG => 0, MREG => 0, PREG => 1)
    port map(
        AB_IN => din0_i_mid,
        C_IN => din0_i,
        ALUMODE_IN => "0011",
        CARRYIN_IN => '0',
        CE_IN => CE,
        CLK_IN => CLK,
        RST_IN => RST,
        P_OUT => din0_i_mid_2 
        ); 
    
    ADDER0 : subadder48
    generic map(ACASCREG => 0, ALUMODEREG => 0, AREG => 0, BCASCREG => 0, BREG => 0, CREG => 0, MREG => 0, PREG => 1)
    port map(
        AB_IN(47) => din0_i_mid_2(47),
        AB_IN(46 downto 0) => din0_i_mid_2(47 downto 1),
        C_IN => do0,
        ALUMODE_IN => "0000",
        CARRYIN_IN => '0',
        CE_IN => CE,
        CLK_IN => CLK,
        RST_IN => RST,
        P_OUT => do0
        ); 
    
    SUBADDER1 : subadder48
    generic map(ACASCREG => 0, ALUMODEREG => 0, AREG => 0, BCASCREG => 0, BREG => 0, CREG => 0, MREG => 0, PREG => 1)
    port map(
        AB_IN => din1_i_mid,
        C_IN => din1_i,
        ALUMODE_IN => "0011",
        CARRYIN_IN => '0',
        CE_IN => CE,
        CLK_IN => CLK,
        RST_IN => RST,
        P_OUT => din1_i_mid_2 
        ); 
    
    ADDER1 : subadder48
    generic map(ACASCREG => 0, ALUMODEREG => 0, AREG => 0, BCASCREG => 0, BREG => 0, CREG => 0, MREG => 0, PREG => 1)
    port map(
        AB_IN(47) => din1_i_mid_2(47),
        AB_IN(46 downto 0) => din1_i_mid_2(47 downto 1),
        C_IN => do1,
        ALUMODE_IN => "0000",
        CARRYIN_IN => '0',
        CE_IN => CE,
        CLK_IN => CLK,
        RST_IN => RST,
        P_OUT => do1
        ); 
    din0_i_mid(47-Len_filter downto 0)    <= do0(47 downto Len_filter); 
    din0_i_mid(47 downto 47-Len_filter+1) <= (others => do0(47));
    din1_i_mid(47-Len_filter downto 0)    <= do1(47 downto Len_filter); 
    din1_i_mid(47 downto 47-Len_filter+1) <= (others => do1(47));
    
    -- enter your statements here --
    --    din0_i(Len_filter downto 0) <= (others => '0');
    --    din0_i(Len_filter+1+15 downto Len_filter+1+0) <= DIN0;
    --    din0_i(48 downto Len_filter+2+15) <= (others => DIN0(15));
    --    din1_i(Len_filter downto 0) <= (others => '0');
    --    din1_i(Len_filter+1+15 downto Len_filter+1+0) <= DIN1;
    --    din1_i(48 downto Len_filter+2+15) <= (others => DIN1(15));
    --    
    --    din0_i_mid(47-Len_filter downto 0)    <= do0(47 downto Len_filter); 
    --    din0_i_mid(48 downto 47-Len_filter+1) <= (others => do0(47));
    --    din1_i_mid(47-Len_filter downto 0)    <= do1(47 downto Len_filter); 
    --    din1_i_mid(48 downto 47-Len_filter+1) <= (others => do1(47));
    --    
    --    din0_i_mid_2 <= din0_i - din0_i_mid;
    --    din1_i_mid_2 <= din1_i - din1_i_mid;
    --    process(CLK)
    --    begin
    --        if rising_edge(CLK) then
    --            if CE = '1' then
    --                do0 <= do0 + din0_i_mid_2(48 downto 1);
    --                do1 <= do1 + din1_i_mid_2(48 downto 1);
    --            end if;
    --        end if;
    --    end process;
    --    
    DOUT0 <= do0(Len_filter+(Len_filter-8)+23 + 1 downto Len_filter+(Len_filter-8)+1);-- + do0(Len_filter+(Len_filter-8));
    DOUT1 <= do1(Len_filter+(Len_filter-8)+23 + 1 downto Len_filter+(Len_filter-8)+1);-- + do1(Len_filter+(Len_filter-8));
    
end filter_Nkx16;
